• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Digital signals, in particular PCM signals, each comprising a number of bits, are converted into analog signals with a R-2R chain network which has series resistors each having a resistance value R and shunt resistors having a resistance value 2R, by feeding a constant current into a connection point between the shunt resistor at one end of the network and the adjacent series resistor. The other end is terminated by the resistor which has a value 2R and, in order to convert a digital signal of a number of bits corresponding to the number of shunt resistors, those ends of the shunt resistors which extend away from the series resistors can be connected, in accordance with the bits of the digital signal, either directly to the base of a constant current source or to a summation current line which is virtually maintained at the same potential and which forms an analog signal output, all the resistors of the network being formed by the source-drain paths of MOS transistors which are integrated on a single chip and which are connected individually and in series and are identical to one another.
    公开号:SU1233820A3
    申请号:SU792807703
    申请日:1979-08-30
    公开日:1986-05-23
    发明作者:Фон Зихарт Фритьоф
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to computing and can be used in information and computing systems, as well as for the connection of computing devices with analogue control objects.
    The purpose of the invention is to increase the accuracy of conversion by reducing the error of the transfer factor of the current divider, with an optimal selection of voltage ratings on the control electrodes of MOS transistors,
    The drawing shows a functional diagram of the device.
    The device comprises a voltage source, a current source 2, an operational amplifier 3 with a resistor 4 in the feedback circuit, n control nodes on switching devices 5, and a n-stage current divider 6 each of which has a cascade 7 in five MOS transistors.
    The first terminal of the first MOS transistor 8 in each stage is connected to the inverting input of the operational amplifier 3, which through a feedback resistor is connected to the other side of the operational amplifier 3, which is the output bus. The second output of the first 8 MOS transistor is connected to the first output of the second 9 MOS transistor, the first output of the third 10 MOS transistor is connected to the zero bus of the current source 2 and the non-inverting input of the operational amplifier 3.
    . The second output of the third 10 MOSFractor is connected to the first output of the fourth 1 MOSFET. The first terminal of the fifth 12 MOS transistor is connected to the second terminals of the second 9 and fourth 1I MOS transistor of the neighboring low-order bit. The second pins of the second 9 and fourth 1 MOS transistors of the higher order are connected to the output bus of the current source 2, and the second output of the fifth 12 MOSFET of the least significant bit is connected to the first pin of the iToro 13 MOS transistor, the second high; The VOD of which is connected to the non-inverting input of the operational amplifier 3. The output of the voltage source 1 is connected to the control terminals of the fifth 12 and sixth 13 MOSFET transistors The input of each switching device 5 is connected to the output of the voltage source 1. The first output of each switching device is connected to the control terminals of the first 8 and second 9 MOS transistors corresponding to the current divider 6 stage. The second output of the switching device 5 is connected to the control terminals of the third 10 and even 1 MOS transistors of the corresponding cascade of the p-cascade current divider 6. The input code N buses are connected to the control inputs of the switching device 5.
    Structurally, the switching device 5 can be performed, for example, on two consecutively connected inverting keys; - in the sist cascades, the output of the second of which is the first code, and
    the output of the first by the second output of the switching device.
    The device works as follows.
    Current. coming from the output of kstatochnikz. 2 current, and the input of the p-cascade current divider 6, is divided into two stages in each stage 7. One part of the current flows through the fifth MOS-tra; a resistor 12 to the input of the next more than a second
    cascade, and each other part of the current depending on the signal (unlocking or locking), g: applied to the traction switches 8-1 1, or just to the test input of the amplifier 3 ,, or paired bus. The remainder of the division of the current through the sixth MOS transistor 13 is supplied to the zero pin.
    The currents arriving at the inverter LPO, and the input of the amplifier 3, are added
    and converted at its output to a voltage. Proportional to the magnitude of the input code, Depending on the value of the code number in the significant digit of the input code N, the output h
    or p.biTeKiieT. Either a current source niHK 2 is emitted at the same time at the output of the device is formed with either flashing or gut-positive fusion.
    The locking output terminal is the same; do not switch, au. |; Its device for 5 is ON, and the unlocking of the output terminal of the voltage source 1, which maintains a constant IOF transistor 2, ic-use of equal the magnitude of the displacement of the voltages on the outputs of the switch switch key: devices 5 and the control of the MOSFETS 12 poses
    It will be possible to achieve high precision of sharing of currents according to the binary law in divider 6 and due to this, to reduce the error of converting the code into an analog signal.
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A device for converting digital signals to their corresponding analog signals, comprising a voltage source, a current source, an operational amplifier with a resistor in the feedback circuit, n control nodes and an n-stage current divider, each stage of which is made in five MOS transistors and in each stage, the pervChA current divider current of the first MOS transistor is connected to an inverting input of an operational amplifier, which is connected via a resistor in the feedback circuit to the output of the operational amplifier and the output bus, sec The first output of the MOS transistor is connected to the first output of the second MOS transistor, the first view of the third MOS transistor is connected to the zero current source and non-inverting input of the operational amplifier, the second output of the third MOS transistor is connected to the first output of the fourth MOS transistor, the first output The nth MOS transistor is connected to the second pins of the second and fourth MOS transistors, the second pin of the pt MOSReditor R. Pitsik
    Compiled by A. Simagin
    Tekhred L.Oleynik Proofreader M. Maximipschnets
    Order 2790/60 Circulation 816 Subscription
    HSPS of the USSR State Committee
    on inventions and open ™ 113035, Moscow, Zh-35, Raushsk nab, 4/5
    Production and printing company, Uzhgorod, st. Project, 4
    2338204
    TpaiisHCTopa is connected to the second you
    ten
    the second and fourth MOS transistors of the upper cascade are connected to the output bus of the current source, the second higher of the youngest cascade is connected to: the first higher-order MOS transistors: one with the first higher-order MOS transistor transistor, coto second output
    The iporo is connected to the non-inverting input of the op amp, the output of the voltage source is connected to the control pins of the fifth and sixth
    MOS transistors are distinguished; in order to increase the conversion accuracy, the control unit is designed as a switching device with one input on two
    Outputs 5 the input of each switching device is connected to the output of the same source of voltage or another source of the same direction {, the first output of each switch is 1, its devices are connected to the control terminals of the first n second MOSFET transistors corresponding of the current cascade of the current divider, the second output of the switching device is connected to the control clues of the third and fourth MOS transistors of the corresponding cascade of the current divider, and the input code is connected to the control inputs of the switching devices roystv.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    FR2043946A5|1969-05-02|1971-02-19|Commissariat Energie Atomique|
    DE2154654C3|1971-11-03|1982-04-15|Siemens AG, 1000 Berlin und 8000 München|Voltage divider circuitry and method of making the same|
    DE2315986C3|1973-03-30|1978-12-14|Siemens Ag, 1000 Berlin Und 8000 Muenchen|Digital-to-analog converter, especially for an iterative coder|
    DE2423130A1|1974-05-13|1975-11-20|Siemens Ag|CIRCUIT ARRANGEMENT FOR CONVERTING DIGITAL SIGANLES, IN PARTICULAR PCM SIGNALS, INTO CORRESPONDING ANALOG VOLTAGES|JPS5312370A|1976-07-20|1978-02-03|Toei Kogyo Kk|Device for automatically and contnuously measuring magnetization curve of magnetic substance|
    DE2939455C2|1979-09-28|1983-11-17|Siemens AG, 1000 Berlin und 8000 München|Circuit arrangement for converting digital signals, in particular PCM signals, into analog signals corresponding to these, with an R-2R chain network|
    JPH0115241Y2|1981-03-20|1989-05-08|
    JPS6351609B2|1982-12-29|1988-10-14|Fujitsu Ltd|
    JPS59163912A|1983-03-08|1984-09-17|Toshiba Corp|C-r type da converter|
    US4580131A|1983-06-03|1986-04-01|Harris Corporation|Binarily weighted D to a converter ladder with inherently reduced ladder switching noise|
    US4635038A|1985-11-08|1987-01-06|Advanced Micro Devices, Inc.|CMOS-transistor-based digital-to-analog converter|
    JPH0449423U|1990-09-03|1992-04-27|
    US5134400A|1991-01-07|1992-07-28|Harris Corporation|Microwave multiplying D/A converter|
    SG44661A1|1992-02-11|1997-12-19|Philips Electronics Nv|Current divider and intergrated circuit comprising a plurality of current dividers|
    JP3222783B2|1996-09-30|2001-10-29|株式会社東芝|D / A converter|
    CN1324320C|2004-04-07|2007-07-04|威盛电子股份有限公司|Multi-pack d.c signal conversion digital signal device|
    JP2007143069A|2005-11-22|2007-06-07|Mitsubishi Electric Corp|Power amplifier|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    DE2838310A|DE2838310C2|1978-09-01|1978-09-01|Circuit arrangement for converting digital signals, in particular PCM signals, into analog signals corresponding to these, with an R-2R chain network|
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